In the present era of very large scale integration, new techniques are needed to more efficiently utilize the space within the semiconductor devices. Certain practical limitations, however, in today's manufacturing process of semiconductors require portions of semiconductor material to be used merely for providing spacing to compensate for such limitations. Such use of semiconductor material occurs in the process of providing interconnecting contacts for the semiconductor devices.
In the manufacture of integrated circuits, interconnecting contacts are provided between the active semiconductive material in which the semiconductor devices are formed, and the interconnect lines. These contacts are typically formed by initially depositing an oxide layer over the top surface of the semiconductor device. A masking layer of photoresist in then provided over the oxide and patterned for exposing the oxide in the contact area. The exposed oxide is then etched, followed by the nonselective deposition of a conducting layer such as aluminum, over the wafer. The conducting layer is then patterned and etched to form the interconnecting contacts.
Inherent in the masking step for patterning the contact area for the base region of a bipolar transistor is the high probability of misaligning the masking layer over the oxide. This misalignment of the masking layer leads to the misalignment of the interconnecting contacts. Addtionally, there exists the potential of overetching the oxide layer during the etching process, which can result in enlarging the size of the contact areas. Either of these occurrences, e.g., the misalignment of the mask or the overetching of the oxide, can short the contacts for the base region with the collector and emitter regions of the semiconductor. To avoid this potential for shorting the base, extra semiconductor material of approximately 2 microns in width is typically provided on each side of the intended location for the contacts such that any potentially misaligned or enlarged contact will be prevented from shorting the collector or emitter regions with the base. This usage of unused active semiconductor area, however, increases the distance of the conductive path from the base contact to the emitter region. This in turn increases the resistance of the base which results in limiting the gain of device unnecessarily. Additionally, the usage of unused active area is a loss of valuable semiconductor real estate which might otherwise be used for additional semiconductor devices.